1. Field of the Invention
The present invention relates to computer IO busses, and more particularly to base IO hardware platforms driving a variable population of IO devices under a variety of protocols and speeds.
2. Background Information
Typical computer systems have a number and variety of input/output (IO) devices attached. Depending on the application these IO devices run from the low speed types measured in seconds (e.g., keyboard entries) to high speed types measured in nanoseconds (e.g., optical communications). The different IO devices may be bit serial or parallel, and the IO may conform to one of a number of standard specifications (e.g., PCI, PCI-x, STD, etc.). Some devices might need to be serviced in real time (music, movies). FIG. 1 shows a typical prior art IO system.
Often the applications break into two types, one that requires one or two very high speed IO channels and a few low or moderate speed channels, and a second type that requires a large number of moderate and low speed devices.
On large symmetrical multiprocessor systems where hundreds of 64-bit processors may be running, clock speed are in the GigaHertz (GHz) range and above and these large systems are being applied to applications requiring large numbers of IO devices including very fast devices. The designers of these system were faced with designing an IO sub-system having a standard IO hardware/firmware platform that is flexible enough to service the variety of devices demanded by a wide range of applications.
At the present time, these IO needs are being met in computer systems by their IO platforms providing a few performance plug-in slots and more medium or low performance plug-in slots. These known IO platform systems strike a tradeoff between a few applications requiring a very high IO bandwidth and a larger number requiring low and/or moderate bandwidth. However, in these systems the total number of slots is fixed and the physical length of the IO bus itself is fixed to extend to all the slots. These facts in themselves limit the IO platforms"" performance for both the high and the low performance IO devices.
FIG. 2A-2D illustrate some of the problems mentioned above. For reference and appreciation of the problems, it is instructive to review what becomes important when GHz speed are used. FIG. 2A shows a typical one GHz clock signal with a period of one nanosecond. The electrical signals along the cable or etched circuit board runs will traverse about six inches in one clock period. In many IO systems and even in large scale integration (LSI) chips distances are measured in inches, so that the transit time of signals on physical runs must be considered when signals are running to and from an IO device controller connected to an IO bus. As discussed below, design of IO systems running in the hundreds of MegaHertz (MHz) speed ranges must be careful of the physical length of the signal runs and the IO device being serviced.
FIG. 2B illustrates the above problems in more detail. In FIG. 2B there are sixty four data signal (D0-D63) that are being delivered to etched runs on a backplane connecting to a number of IO controller slots. In this example, the runs are multiplexed sharing data and address out to the IO devices. In addition, the data paths are bidirectional and for purposes of this discussion the timing and load issues are discussed herein for D0 the data out lines. The general considerations, however, apply for data in, control signals in and out, and for clock signals. Referring to FIG. 2B, when the signals appear on the bus they will be physically routed to one of several IO controllers attached to the bus. One controller 6 may be in slot 1, and the data, here illustrated with one data line D0, is presented eventually (there could be logic involved in the general case) to a data flop 32 or another such storage device, and, after the time delay of the backplane, the same data will be presented to a data flop 34 in the farthest slot n.
FIG. 2C details the transit delays. The Data Enable places D0 on the backplane at A as shown. D0 appears at E after the time delay determined by the time distance along the backplane 36 from A to E. D0 appears at the data flop 32 that is positioned is as close to the bus as practical. The D0 signal continues travelling down the backplane until point F the end is reached. Regardless of the loads on the bus (assuming high impedance loads and no transmission line terminations) the D0 signal will incur a full position reflection 38 at location F since the bus is open circuited. That reflection will travel back to location E 30 exhibiting an overshoot 40 and finally to the source A where, if the gate 18 presents a low impedance (from a driver), a negative reflection occurs which then travels back down the bus. These signals travel back and forth causing oscillations of a frequency determined from the time length of the backplane busxe2x80x94a quarter wave length tuned circuit. In a practical embodiment where the backplane length is about one foot (2 nanoseconds) long, the ringing oscillation 42 in FIG. 2D on a step function signal will be of about an eight nanosecond period or one hundred and twenty-five MHz (125 MHz). This is right in the range of IO clock speeds in many practical systems. Since reflection must be reasonable settled on data, address and clock signals before the signal can be reliably latched, the IO performance may be limited in practical system by such ringing. It should be noted that capacitors may be found on the lines which are intended to reduce any such ringing.
As shown in FIG. 2B, the clock signal 16 is designed to exhibit the same delays travelling down the bus as the data, so that the clock (clock forwarding) and the data arrive at about the same time thereby compensating for the bus delay.
Another issue for the IO sub-system design is illustrated in FIG. 2B, where the number and type of IO controllers and devices are not known. Referring back to FIG. 1, it is evident that if the speed of the computer to Bus Controller 2 is known, say one GHz, then the combination of all the IO devices connected to the bus controller cannot sustain more than a one GHz IO speed (buffering may help in some limited special applications). The bus controller can only support a given number of devices depending on the number of such devices and their speeds (and the number of slots). More over, if too many fast devices are attached to the IO bus, the system must run slower in accordance with these IO devices, and the IO devices will have to wait for service.
The low performance is limited in that there are not enough slots for some applications.
There is a need for a flexible IO platform that provides a high speed bus whose speed is not substantially limited by the physical bus length, and wherein the same platform is flexible to accommodate a number of mid and low speed IO devices.
The above objects and the limitations of the prior art are satisfied by the following programmable IO hardware and method.
The present invention provides switches that are placed along an IO bus adjacent to connectors or sockets or similar means for attaching a device controller to the IO bus. The bus may be preferably embodied as etched printed circuit runs along a backplane, or as wires or cables or similar such embodiments as are known in the art. The switches lengthen or shorten the actual bus length as determined from signals sent out by the processor system to which the IO bus is attached. The processor system is apprised of the location along the bus of and shortens the bus length to accommodate the farthest IO device controller. In a preferred embodiment, the IO device controllers are placed at the nearest (electrically nearest) to the processing system. In this embodiment the number of IO device controllers is made known to or are determined by the processor system, then the processing system system assumes those IO controllers are placed in the nearest IO slots. The processor system shortens the physical length of the bus to those necessary IO slots.
The number, speed and type of IO controller are also made known to or determined by the processor system, whereupon the processor system will determine the speed of the IO bus in order to accommodate the IO controllers. Preferably the number, speed and type are made known to the processing system by use of pins or connections made to IO device controllers or by the initialization process designed for the system. Preferably many IO bus standards provide this capability, or the ability is provided by specially designed hardware and/or software. In a preferred embodiment, the IO speed is operated at the speed of the slowest device attached to the IO bus.